Design-Reuse

Designing Using the AMBA (TM) 3 AXI (TM) Protocol -- Easing the Design Challenges and Putting the Verification Task on a Fast Track to Success

The need for higher performance applications is driving the requirement for a new age of on-chip communication infrastructure. Increasing the clock frequency no longer addresses this higher ...
Design-Reuse

Averant Announces AMBA AXI Protocol Checker

Alameda, Calif. – June 2, 2005 – Averant Inc., a leading provider of advanced design verification technology for RTL designers, today announced the release of the SolidPC™ protocol checker for ...
EDN

Self-timed interconnect solution supports AXI bus protocol

SAN FRANCISCO — EDA and intellectual property (IP) startup Silistix Ltd. has added support for the on-chip AMBA AXI bus protocol to the company's synthesized self-timed interconnect technology, ...
EDN

Verification IP on AMBA:APB,AHB,AXI

The Perfectus VIP for AXI, AHB, APB provides an efficient algorithm to verify the AMBA based designs by giving the advance techniques including the support for System Verilog assertions. AXI ...
Business Wire

PLDA Announces Two Innovative vDMA Engine IP Solutions, Delivering Robust Performance and Scalability across a PCIe Link or AMBA AXI Fabric

SAN JOSE, Calif.--(BUSINESS WIRE)--PLDA, the industry leader in PCI Express® IP solutions, today announced two innovative DMA engine solutions designed to manage large and heterogeneous data traffic ...
Electronic Design

Formal Techniques for Protocol Verification: A Case Study On Verifying the ARM ACE Protocol

More processors on SoCs means more sophisticated cache control. This article describes formal techniques for verifying cache coherency for the ARM AMBA AXI Coherency Extensions (ACE) protocol. Fig 1.